1. Field of the Invention
The present invention relates to the optimization of a cache allocate store strategy when stores are performed in the supervisor mode.
2. Art Background
In a computer system, the speed of computer operations may be restricted by the speed of memory accesses. To increase the speed of memory accesses, caches were developed. A cache is a high-speed memory that stores a portion of the main memory that is being accessed by the computer system. Caches take advantage of the fact that accesses to memory experience locality, that is, accesses occur to memory to repetitive addresses or addresses that are local, that is, for example, within the same page. Thus, by copying certain portions of memory accessed into this cache, there is a likelihood that subsequent accesses to main memory will be found already stored in the cache for quick access.
A number of techniques are used for maintaining the cache and updating the cache and the memory to be consistent to one another. These various techniques are well known in the art, see for example, John L. Hennessey and David A. Patterson, Computer Architecture - A Quantitative Approach (Morgan Kaufmann Publishers Inc. 1990), pages 408-425.
There are typically two policies that exist for write operations to the cache. One is the write through policy (also referred to as store through), wherein the information to be written is written to both a block of the cache and the block of the memory, and the write back policy (also referred to as copy back or store in), in which the information is written all into the block in the cache and the modified cache block is written to main memory only when that cache block is replaced from the cache. Both techniques have their advantages. Using the write through policy, main memory is identified to have the most current copy of the data. This is quite important for cache consistency. Furthermore, it is also the easier of the two policies to implement. However, the CPU must wait for the write operations to complete during write throughs, resulting in a CPU write stall. One optimization to reduce write stall is a write buffer, which allows the processor to continue while the memory is being updated. As the data is stored in the write buffer, the operation to the cache is performed by accessing the data from the write buffer, eliminating the need for the CPU to wait until the write to the cache is complete.
If a miss occurs on a write operation, there are typically two options or techniques to perform. In the write allocate technique (also referred to as fetch on write), the block of data is loaded into the main memory and subsequently loaded into the cache. In a no write allocate system, the block is modified in the memory and not loaded into the cache. The write allocate process is desirable for cache consistency purposes. Furthermore, taking into consideration locality, there is a strong likelihood that that same memory will be subsequently accessed. Therefore, the time penalty incurred in updating the memory and the data cache is well offset by the time savings achieved when subsequently accessing the data cache for the same or local data.
Data locality, however, is not a common occurrence when the write operations are performed while in supervisor mode. These write operations typically include operating system, or kernel type operations, such as initializing a page in memory. Supervisor subroutines to perform certain supervisor operations may include supervisor instructions or user instructions. By their nature, these type of operations, performed while in supervisor mode, do not require or indicate that a subsequent read would be performed in a timely manner to make the time penalty paid for updating the cache worth the expense. Although pages can be marked as non-cacheable so that the load to the cache is not performed on a store operation, these pages are frequently accessed by not only the supervisor, but by the user. For user access, it is desirable these pages are cacheable such that time savings are achieved, due to the locality of data accesses during user operations.